The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Conventional memory devices, such as single port memory device capable of supporting only a single memory operation, such as write operation, in a single clock cycle often suffer from limited write memory capacity that may be insufficient for some applications. For example, in the context of network switching, such memory devices may be employed by a switching device for buffering packets during processing of the packets by the switching device, or for storing information (e.g., metering data) determined for packets during processing of the packets by the network device. In such applications, memory devices require sufficient write capacity to be able to operate at the wire speed rate of network ports. Increasing wire speed rates, therefore, require memories with increasingly high write capacities. However, conventional methods of increasing write capacity of a memory device are inefficient and require significant increases in area occupied by the memory device and/or power consumed by the memory device. Further, the conventional methods are not easily scalable for higher memory capacities.